1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More specifically, the present invention is in the field of fabrication of semiconductor memory arrays.
2. Background Art
Semiconductor data arrays, such as read-only-memory (“ROM”) arrays, include bit cells, which are arranged in rows and columns. In a ROM array, for example, the bit cells can be situated between active lines, which form a ground bus. The bit cells, which can comprise two-bit stacks, can be accessed by word lines and columns. The size of the ROM array is determined by the size of the bit cells within the ROM array. Thus, in order to satisfy an increasing demand for reduced-size semiconductor devices that include semiconductor data arrays, such as ROM arrays, semiconductor manufacturers are challenged to reduce the size of the bit cells within these arrays.
The size of the bit cells in a typical semiconductor data array, such as a ROM array, is determined by dimensions such as active line width, word line width, contact width, and spacing between active and word lines and contacts. However, since these dimensions in current bit cells are generally close to minimum dimensions allowable by design rules, it is difficult to decrease bit cell size.
Additionally, it is desirable to increase speed, manufacturing yield, and/or manufacturing robustness of bit cells in semiconductor data arrays, such as ROM arrays.
Thus, there is need in the art for a bit cell having reduced size in a semiconductor data array, such as a ROM array. There is further need in the art for a bit cell having increased speed and manufacturing yield.